Publications

PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs

In recent years, there has been increasing adoption of FPGAs in datacenters as hardware accelerators, where a large population of end …
Moazin Khatti, Xingyu Tian, Yuze Chi, Licheng Guo, Jason Cong, Zhenman Fang
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RapidStream 2.0: Automated Parallel Implementation of Latency Insensitive FPGA Designs Through Partial Reconfiguration

FPGAs require a much longer compilation cycle than conventional computing platforms like CPUs. In this paper, we shorten the overall …
Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Eddie Hung, Wuxi Li, Jason Lau, Weikang Qiao, Yuze Chi, Linghao Song, Yuanlong Xiao, Alireza Kaviani, Zhiru Zhang, Jason Cong
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SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs

Stencil computation is one of the fundamental computing patterns in many application domains such as scientific computing and image …
Xingyu Tian, Zhifan Ye, Alec Lu, Licheng Guo, Yuze Chi, Zhenman Fang
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Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver

The continued growth in the processing power of FPGAs coupled with high bandwidth memories (HBM), makes systems like the Xilinx U280 …
Linghao Song, Licheng Guo, Suhail Basalama, Yuze Chi, Robert F. Lucas, Jason Cong
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Democratizing Domain-Specific Computing

Creating a programming environment and compilation flow that empowers programmers to create their own DSAs efficiently and affordably …
Yuze Chi, Weikang Qiao, Atefeh Sohrabizadeh, Jie Wang, Jason Cong
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TARO: Automatic Optimization for Free-Running Kernels in FPGA High-Level Synthesis

Streaming applications have become one of the key application domains for high-level synthesis (HLS) tools. For a streaming …
Young-kyu Choi, Yuze Chi, Jason Lau, Jason Cong
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Serpens: A High Bandwidth Memory Based Accelerator for General-Purpose Sparse Matrix-Vector Multiplication

Sparse matrix-vector multiplication (SpMV) multiplies a sparse matrix with a dense vector. SpMV plays a crucial role in many …
Linghao Song, Yuze Chi, Licheng Guo, Jason Cong
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PYXIS: An Open-Source Performance Dataset Of Sparse Accelerators

Customized accelerators provide gains of performance and efficiency in specific domains of applications. Sparse data structures and/or …
Linghao Song, Yuze Chi, Jason Cong
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StreamGCN: Accelerating Graph Convolutional Networks with Streaming Processing

While there have been many studies on hardware acceleration for deep learning on images, there has been a rather limited focus on …
Atefeh Sohrabizadeh, Yuze Chi, Jason Cong
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Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication

Sparse-Matrix Dense-Matrix multiplication (SpMM) is the key operator for a wide range of applications including scientific computing, …
Linghao Song, Yuze Chi, Atefeh Sohrabizadeh, Young-kyu Choi, Jason Lau, Jason Cong
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RapidStream: Parallel Physical Implementation of FPGA HLS Designs

FPGAs require a much longer compilation cycle than conventional computing platforms like CPUs. In this paper, we shorten the overall …
Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Jie Wang, Yuze Chi, Weikang Qiao, Alireza Kaviani, Zhiru Zhang, Jason Cong
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Accelerating SSSP for Power-Law Graphs

The single-source shortest path (SSSP) problem is one of the most important and well-studied graph problems widely used in many …
Yuze Chi, Licheng Guo, Jason Cong
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Design Automation and Optimization for Memory-Bound Application Accelerators

As we witness the breakdown of Dennard scaling, we can no longer get faster computers by shrinking transistors without increasing power …
Yuze Chi
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Recut: a Concurrent Framework for Sparse Reconstruction of Neuronal Morphology

Advancement in modern neuroscience is bottlenecked by neural reconstruction, a process that extracts 3D neuron morphology (typically in …
Karl Marrett, Muye Zhu, Yuze Chi, Chris Choi, Zhe Chen, Hong-Wei Dong, Chang Sin Park, X. William Yang, Jason Cong
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SPA-GCN: Efficient and Flexible GCN Accelerator with an Application for Graph Similarity Computation

While there have been many studies on hardware acceleration for deep learning on images, there has been a rather limited focus on …
Atefeh Sohrabizadeh, Yuze Chi, Jason Cong
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Extending High-Level Synthesis for Task-Parallel Programs

C/C++/OpenCL-based high-level synthesis (HLS) becomes more and more popular for field-programmable gate array (FPGA) accelerators in …
Yuze Chi, Licheng Guo, Jason Lau, Young-kyu Choi, Jie Wang, Jason Cong
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HBM Connect: High-Performance HLS Interconnect for FPGA HBM

With the recent release of High Bandwidth Memory (HBM) based FPGA boards, developers can now exploit unprecedented external memory …
Young-kyu Choi, Yuze Chi, Weikang Qiao, Nikola Samardzic, Jason Cong
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AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs

Despite an increasing adoption of high-level synthesis (HLS) for its design productivity advantages, there remains a significant gap in …
Licheng Guo, Yuze Chi, Jie Wang, Jason Lau, Weikang Qiao, Ecenur Ustun, Zhiru Zhang, Jason Cong
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When HLS Meets FPGA HBM: Benchmarking and Bandwidth Optimization

With the recent release of High Bandwidth Memory (HBM) based FPGA boards, developers can now exploit unprecedented external memory …
Young-kyu Choi, Yuze Chi, Jie Wang, Licheng Guo, Jason Cong
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Exploiting Computation Reuse for Stencil Accelerators

Stencil kernel is an important type of kernel used extensively in many application domains. Over the years, researchers have been …
Yuze Chi, Jason Cong
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Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency

Designs generated by high-level synthesis (HLS) tools typically achieve a lower frequency compared to manual RTL designs. In this work, …
Licheng Guo, Jason Lau, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang, Jason Cong
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HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration

The domain-specific language (DSL) for image processing, Halide, has generated a lot of interest because of its capability of …
Jiajie Li, Yuze Chi, Jason Cong
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FLASH: Fast, ParalleL, and Accurate Simulator for HLS

A large semantic gap between a high-level synthesis (HLS) design and a low-level RTL simulation environment often creates a barrier for …
Young-kyu Choi, Yuze Chi, Jie Wang, Jason Cong
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Rapid Cycle-Accurate Simulator for High-Level Synthesis

A large semantic gap between the high-level synthesis (HLS) design and the low-level (on-board or RTL) simulation environment often …
Yuze Chi, Young-kyu Choi, Jason Cong, Jie Wang
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HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing

With the pursuit of improving compute performance under strict power constraints, there is an increasing need for deploying …
Yi-Hsiang Lai, Yuze Chi, Yuwei Hu, Jie Wang, Cody Hao Yu, Yuan Zhou, Jason Cong, Zhiru Zhang
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SODA: Stencil with Optimized Dataflow Architecture

Stencil computation is one of the most important kernels in many application domains such as image processing, solving partial …
Yuze Chi, Jason Cong, Peng Wei, Peipei Zhou
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GraphH: A Processing-in-Memory Architecture for Large-scale Graph Processing

Large-scale graph processing requires the high bandwidth of data access. However, as graph computing continues to scale, it becomes …
Guohao Dai, Tianhao Huang, Yuze Chi, Jishen Zhao, Guangyu Sun, Yongpan Liu, Yu Wang, Yuan Xie, Huazhong Yang
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An Optimal Microarchitecture for Stencil Computation with Data Reuse and Fine-Grained Parallelism

Stencil computation is one of the most important kernels for many applications such as image processing, solving partial differential …
Yuze Chi, Peipei Zhou, Jason Cong

ForeGraph: Exploring Large-scale Graph Processing on Multi-FPGA Architecture

The performance of large-scale graph processing suffers from challenges including poor locality, lack of scalability, random access …
Guohao Dai, Tianhao Huang, Yuze Chi, Ningyi Xu, Yu Wang, Huazhong Yang
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FPGP: Graph Processing Framework on FPGA A Case Study of Breadth-First Search

Large-scale graph processing is gaining increasing attentions in many domains. Meanwhile, FPGA provides a power-efficient and highly …
Guohao Dai, Yuze Chi, Yu Wang, Huazhong Yang
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NXgraph: An Efficient Graph Processing System on a Single Machine

Recent studies show that graph processing systems on a single machine can achieve competitive performance compared with cluster-based …
Yuze Chi, Guohao Dai, Yu Wang, Guangyu Sun, Guoliang Li, Huazhong Yang
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Test–Retest Reliability of Graph Metrics in High-resolution Functional Connectomics: A Resting-State Functional MRI Study

Background: The combination of resting-state functional MRI (R-fMRI) technique and graph theoretical approaches has emerged as a …
Hai‐Xiao Du, Xu‐Hong Liao, Qi‐Xiang Lin, Gu‐Shu Li, Yu‐Ze Chi, Xiang Liu, Hua‐Zhong Yang, Yu Wang, Ming‐Rui Xia
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