Avatar

Yuze Chi

Biography

Yuze Chi (Blaok) obtained his PhD in Computer Science Department, UCLA. Yuze has been working on various software/hardware optimization projects in many big data applications, including graph processing, image processing, and genomics. Beyond building accelerators for each application one by one, Yuze also worked on unified programming infrastructures for heterogeneous systems. After graduation, Yuze joined Google and started the quest to handle and optimize network traffic at Google scale.

Interests

  • Heterogeneous Systems
  • Hardware Acceleration
  • Big Data Optimization
  • Cloud Computing

Education

  • Ph.D., Compute Science, 2016–2021

    University of California, Los Angeles

  • B.E., Electronic Engineering, 2012–2016

    Tsinghua University

Publications

Accelerating SSSP for Power-Law Graphs. In FPGA, 2022.

PDF Code

RapidStream: Parallel Physical Implementation of FPGA HLS Designs. In FPGA, 2022.

PDF Code

Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication. In FPGA, 2022.

PDF Code

Extending High-Level Synthesis for Task-Parallel Programs. In FCCM, 2021.

PDF Code Slides Video

AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs. In FPGA (Best Paper Award), 2021.

PDF Code Slides Video

HBM Connect: High-Performance HLS Interconnect for FPGA HBM. In FPGA, 2021.

PDF Slides Video

When HLS Meets FPGA HBM: Benchmarking and Bandwidth Optimization. In arXiv, 2020.

PDF

Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. In DAC, 2020.

PDF Code Slides Video

FLASH: Fast, ParalleL, and Accurate Simulator for HLS. In TCAD, 2020.

PDF

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing. In FPGA (Best Paper Award), 2019.

PDF Code Slides

Rapid Cycle-Accurate Simulator for High-Level Synthesis. In FPGA, 2019.

PDF Slides

SODA: Stencil with Optimized Dataflow Architecture. In ICCAD (Best Paper Candidate), 2018.

PDF Code Slides

GraphH: A Processing-in-Memory Architecture for Large-scale Graph Processing. In TCAD, 2018.

PDF

ForeGraph: Exploring Large-scale Graph Processing on Multi-FPGA Architecture. In FPGA, 2017.

PDF Slides

FPGP: Graph Processing Framework on FPGA A Case Study of Breadth-First Search. In FPGA, 2016.

PDF Slides

NXgraph: An Efficient Graph Processing System on a Single Machine. In ICDE, 2016.

PDF Slides

Test–Retest Reliability of Graph Metrics in High-resolution Functional Connectomics: A Resting-State Functional MRI Study. In CNSNT, 2015.

PDF

Teaching

I am a teaching assistant for the following courses at UCLA:

  • CS180: Introduction to Algorithms and Complexity, Fall 2017
  • CS259: Customized Computing for Big-Data Applications, Fall 2018
  • CS133: Parallel and Distributed Computing, Winter 2019