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Yuze Chi

Biography

Yuze Chi (Blaok) obtained his PhD in Computer Science Department, UCLA. Yuze has been working on various computer system optimization projects in many big data applications, including graph processing, image processing, and genomics. Beyond building optimized solutions for each application one by one, Yuze also worked on unified programming infrastructures for heterogeneous systems. After graduation, Yuze joined Google and started the quest to handle and optimize computing and networking infrastructures at Google scale.

Interests

  • Heterogeneous Systems
  • Hardware Acceleration
  • Big Data Optimization
  • Cloud Computing

Education

  • Ph.D., Compute Science, 2016–2021

    University of California, Los Angeles

  • B.E., Electronic Engineering, 2012–2016

    Tsinghua University

Publications

PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs. In FCCM, 2023.

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RapidStream 2.0: Automated Parallel Implementation of Latency Insensitive FPGA Designs Through Partial Reconfiguration. In TRETS, 2023.

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Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver. In FPGA, 2023.

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Democratizing Domain-Specific Computing. In CACM, 2022.

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TARO: Automatic Optimization for Free-Running Kernels in FPGA High-Level Synthesis. In TCAD, 2022.

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PYXIS: An Open-Source Performance Dataset Of Sparse Accelerators. In ICASSP, 2022.

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StreamGCN: Accelerating Graph Convolutional Networks with Streaming Processing. In CICC, 2022.

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Accelerating SSSP for Power-Law Graphs. In FPGA, 2022.

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RapidStream: Parallel Physical Implementation of FPGA HLS Designs. In FPGA, 2022.

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Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication. In FPGA, 2022.

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Recut: a Concurrent Framework for Sparse Reconstruction of Neuronal Morphology. In bioRxiv, 2021.

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Extending High-Level Synthesis for Task-Parallel Programs. In FCCM, 2021.

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HBM Connect: High-Performance HLS Interconnect for FPGA HBM. In FPGA, 2021.

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AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs. In FPGA (Best Paper Award), 2021.

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When HLS Meets FPGA HBM: Benchmarking and Bandwidth Optimization. In arXiv, 2020.

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Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. In DAC, 2020.

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FLASH: Fast, ParalleL, and Accurate Simulator for HLS. In TCAD, 2020.

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HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing. In FPGA (Best Paper Award), 2019.

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Rapid Cycle-Accurate Simulator for High-Level Synthesis. In FPGA, 2019.

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SODA: Stencil with Optimized Dataflow Architecture. In ICCAD (Best Paper Candidate), 2018.

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GraphH: A Processing-in-Memory Architecture for Large-scale Graph Processing. In TCAD, 2018.

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ForeGraph: Exploring Large-scale Graph Processing on Multi-FPGA Architecture. In FPGA, 2017.

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FPGP: Graph Processing Framework on FPGA A Case Study of Breadth-First Search. In FPGA, 2016.

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NXgraph: An Efficient Graph Processing System on a Single Machine. In ICDE, 2016.

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Test–Retest Reliability of Graph Metrics in High-resolution Functional Connectomics: A Resting-State Functional MRI Study. In CNSNT, 2015.

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Teaching

I am a teaching assistant for the following courses at UCLA:

  • CS180: Introduction to Algorithms and Complexity, Fall 2017
  • CS259: Customized Computing for Big-Data Applications, Fall 2018
  • CS133: Parallel and Distributed Computing, Winter 2019